QuickLogic’s ArcticPro 3 embedded FPGA (eFPGA) IP is now available on Samsung’s 28nm FD–SOI process. This enables OEMs and semiconductor companies to seamlessly integrate the capability of discrete FD-SOI FPGAs into their own ASICs/SoCs to optimiseg system performance, power consumption and cost for edge AI in consumer, IoT and automotive applications.
Automotive
Research indicates Pohoiki Beach chip for neural-inspired algortithms
An eight million neuron system, comprised of 64 Phokiki Beach chips, the codename for Loihi chips, is now available to the research community. The neuromorphic system will allow researchers to experiment with Lohi, Intel’s brain-inspired research chip, which applies the principles found in biological brains to computer architectures. Loihi enables users to process information up to 1,000 times faster and 10,000 times more efficiently than CPUs for specialised applications like sparse coding, graph search and constraint-satisfaction problems.
Cadence claims DisplayPort 2.0 verification IP is first to market
Driving early adoption of the next-generation DisplayPort standard for mobile and automotive applications, Cadence Design Systems claims to offer the industry’s first Verification IP (VIP) in support of the new DisplayPort 2.0 standard. The Cadence VIP for DisplayPort 2.0 enables designers to quickly and thoroughly complete the functional verification of their mobile, audio visual and augmented reality/virtual reality (AR/VR) system-on-chip (SoC) designs with assurance that the design will operate as expected.
Cadence releases design flow and sign-off tools for Cortex-A77
Following the announcement by Arm of the Cortex-A77 CPU, Cadence has followed up quickly, with full-flow digital and sign-off tools optimised for this processor.
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