Cadence claims DisplayPort 2.0 verification IP is first to market
Driving early adoption of the next-generation DisplayPort standard for mobile and automotive applications, Cadence Design Systems claims to offer the industry’s first Verification IP (VIP) in support of the new DisplayPort 2.0 standard. The Cadence VIP for DisplayPort 2.0 enables designers to quickly and thoroughly complete the functional verification of their mobile, audio visual and augmented reality/virtual reality (AR/VR) system-on-chip (SoC) designs with assurance that the design will operate as expected.
The Cadence VIP for DisplayPort 2.0 has been architected to meet the specifications of the new standard—enhancing design verification productivity, ensuring high-quality designs and delivering maximum performance. It offers the industry’s most comprehensive protocol validation solution for DisplayPort designs and includes a configurable bus functional model (BFM), a protocol monitor and a library of integrated protocol checks to optimise verification predictability. The VIP has been designed for easy integration into testbenches at IP, SoC and system levels, helping engineers reduce time to first test and accelerate verification closure.
“By releasing the first-to-market VIP for DisplayPort 2.0, we’re enabling early adopters to ensure their designs comply with the specification while achieving the fastest path to IP verification closure,” said Paul Cunningham, corporate vice president and general manager of the System & Verification Group at Cadence. “We have been working closely with early adopters of the spec, which has enabled us to provide a solid and high-quality verification IP for advanced designs for automotive, mobile and machine learning applications.”
The VIP extends the Cadence Verification IP portfolio which is part of the broader Cadence Verification Suite. It is optimised for Xcelium Parallel Logic Simulation, and supported third-party simulators. The Verification Suite comprises best-in-class core engines and verification fabric technologies to increase design quality and throughput, says Cadence.
The Cadence Verification IP supports the company’s Intelligent System Design strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently.
