Consortium develops programmable binaural hearing aid SoC
The programmability of a prototype binaural hearing aid SoC enables developers to create hearing aids which process critical sounds optimally while simultaneously reducing background noise.
The prototype was developed by a consortium consisting of Cadence Design Systems, GlobalFoundries, Hoerzentrum Oldenburg and Leibniz University Hannover. The Smart Hearing Aid Processor (SmartHeAP) SoC is based on the Cadence Tensilica Fusion G6 DSP and Tensilica Xtensa LX7 processor, the Cadence digital full flow and the GF 22FDX platform.
The SoC prototype provides hearing aid companies with all the components required to create and reprogramme hearing devices that improve a wearer’s hearing experience. For example, the binaural hearing technology means that hearing aids in the right and left ears communicate with one another, enabling a wearer to pick up sounds from the full auditory scene without destroying the binaural cues.
The SoC also improves hearing loss compensation capabilities. Using advanced algorithms the SoC automatically analyses the incoming signal and provides adaptive sound amplification that is customised to the wearer’s unique hearing needs.
The SoC is designed to provide high processing capacity with minimal power consumption in order to extend hearing aid battery life. In addition, the hearing aid software can be quickly upgraded without replacing the hardware, saving both the wearers and the hearing aid companies money.
The level of programming languages is designed to accelerate time to market.
The Tensilica Fusion G6 is an easy-to-program, multi-purpose DSP that provides low energy consumption and a small footprint, said Cadence. The Tensilica Xtensa LX7 processor is tailored for control-intensive tasks and also offers a small footprint. The Cadence digital full flow enables a fast path to design closure and better predictability while delivering optimal, power, performance and area (PPA), said the company. Its GF 22FDX platform provides up to 50 per cent lower power at the same high performance frequencies, compared to 28nm processes. Thiis is enabled by the adaptive body bias (ABB) feature, which is critically important for low 0.5V VDD or below to reduce power consumption on battery-powered devices, such as hearing aids, advised Cadence.
The SmartHeAP project is supported by the German Federal Ministry of Education and Research under grant 16ES0760.