CEVA streamlines 5G NR modem design to accelerate time to market
The second generation 5G architecture by Ceva, PentaG2, has been announced by wireless connectivity and smart sensing technology specialist, Ceva.
PentaG2 is a comprehensive hardware / software IP platform that combines advanced DSPs with special purpose accelerators for optimal signal chain processing, to deliver a four-fold improvement in power efficiency versus its predecessor, claimed Ceva.
PentaG2 includes programmable accelerators and coprocessors, and introduces accelerations such as a bit demodulation unit, supporting entire Rx bit and LLR processing and one for Tx bit processing, an equaliser and MAC engine co-processor unit together with a 5G LDPC encoder / decoder and a 5G polar encoder / decoder.
Other hardware accelerators include HARQ, MLD, Multi-radix DFT, Turbo FEC and Viterbi FEC, and a neural network coprocessor for 5G link adaptation. All accelerators come with standard AXI. The platform also includes a scalar DSP for PHY control, hardware acceleration scheduling, and running the protocol stack. The PentaG2-Max also features a vector DSP with 5G ISA extensions for handling workloads required for channel estimation.
There is also a complete L1 SW functional implementation of all 5G processing chains, running on the control DSP and using all the platform’s hardware accelerators, including PDSCH, PUSCH, PDCCH and PUCCH.
An advanced platform System-C simulation environment allows system engineers, architects and software developers to model, profile and debug designs, pre-silicon. This simulator supports all PentaG2 components and interfaces seamlessly with MATLAB for algorithmic development. The whole PentaG2 system can be emulated on a FPGA platform for further verification.
The architecture is aimed at accelerating the proliferation of new usage models for mobile broadband and IoT, and to reduce the entry barriers for handset OEMs looking to internalise 5G modem design.
According to Ceva, PentaG2 substantially lowers the high entry barriers for semiconductor companies and OEMs in the 5G mobile broadband and IoT market as well as for 5G handset SoCs.
There are initially two configurations of PentaG2. PentaG2-Max targets eMBB use cases in handsets and CPE/FWA terminals and mmWave, NR-Sidelink and cellular V2X (C-V2X), as well as URLLC enabled AR/VR use cases. It is claimed to be the only complete IP offering able to efficiently process the immense workloads required for 3GPP releases 16 and 17, as well as 5G advanced, for both Sub-6 and mmWave 5G broadband, with a four fold performance/area improvement in data path processing.
PentaG2-Lite supports a range of reduced capacity use cases, including LTE Cat1 and future 3GPP Rel-17/18 NR RedCap (reduced capacity, or NR-Lite). This configuration is described by Ceva as an efficient and lean baseband implementation with complete processing chain acceleration. It uses a small footprint DSP controller, to meet the most stringent power budgets.
Both configurations offer the flexibility to allow customers combine their own proprietary algorithms and IP, such as channel estimation or advanced equalisation with the PentaG2 platform via standard interfaces.
PentaG2 is available for licensing to lead customers today and for general licensing in the second half of this year.
