Cadence introduces software for reliable automotive, medical IC design

Addressing reliability challenges across the product lifecycle for automotive, medical, industrial, aerospace and defence applications, Cadence Design Systems introduces the Cadence Legato Reliability Solution. It targets the design of high-reliability analogue and mixed-signal ICs for automotive, medical, industrial, and aerospace and defence applications. The Legato Reliability Solution tools manage designs throughout the product lifecycle, from initial test through active life through aging.

It is based on the Cadence Spectre Accelerated Parallel Simulator and the Cadence Virtuoso custom IC design platform, and integrates capabilities into an intuitive cockpit for the three phases of the product lifecycle. These are analogue defect analysis, which accelerates defect simulation by up to 100X, reducing test cost and eliminating test escapes, electro-thermal analysis to avoid premature failures due to thermal overstress during the product’s useful life, and advanced aging analysis, which enables accurate prediction of product wear-out by analysing aging acceleration due to temperature and process variation.

Tom Beckley, Cadence senior vice president and general manager, custom IC and PCB group explained the rationale behind the software introduction. “Designers are faced with the challenge of designing across the entire lifecycle, including eliminating the test escapes that become field failures early in the life cycle, preventing thermal overstress from operating in extreme conditions like under the hood of a car, and designing for 15 years or more of operating lifetime. Our new Legato Reliability solution enables designers to answer these critical questions much earlier in the design process.”

Cadence introduces a simulation engine to enable a new test methodology for analogue ICs – defect-oriented testing – that expands the capabilities of test beyond what is achievable with functional and parametric tests. Defect-oriented testing allows designers to evaluate the ability to eliminate die with manufacturing defects and resulting test escapes that cause field failures. It can also be used to optimise wafer test, reducing the number of tests required to achieve the target defect coverage by eliminating over-testing and potentially reducing the number of tests up to 30 per cent. Customer experience with the tool indicates that it accelerates defect simulation by more than 100X.

The company is introducing a dynamic electro-thermal simulation engine with this release. For automotive designers, for example, actual usage results in significant temperature rise during normal operation due to on-chip losses and power dissipated in the switches. In addition, these components need to operate in hostile environments. The combination of high-power dissipation in a high-temperature environment can result in thermal overstress that can result in failure during normal operation. Dynamic electro-thermal simulation allows designers to simulate the on-chip temperature rise and validate the operation of over-temperature protection circuits.   

Cadence is enhancing aging analysis to include the effects that accelerate device wear-out including temperature and process variation. It also provides a new aging model for device degradation in advanced nodes with FinFET transistors.

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