Cadence digital and custom tool suite is optimised for TSMC’s 3nm process
The collaboration between Cadence and TSMC has broadened as the partners announce that the former’s digital full flow and custom tool suite has been optimised for TSMC’s 3nm (N3) process technology.
The Cadence tools have achieved the latest design rule manual (DRM) and Spice certification for the N3 process. These innovations assist in driving and delivering next-generation mobile, artificial intelligence (AI) and high performance computing (HPC) applications, developed on the N3 process technology, says Cadence, with reference flows and methodologies.
Customers can download the corresponding N3 process design kit (PDK) to begin design projects now.
The updated digital full flow for N3, features enhanced physical optimisation and timing signoff closure. It includes the Innovus Implementation System, Liberate Characterisation, Liberate Variety Statistical Characterisation, Quantus Extraction Solution, Tempus Timing Signoff Solution, Voltus IC Power Integrity and Pegasus Verification System. In addition, the Genus Synthesis and its predictive iSpatial technology is enabled for these process technologies for mobile, AI and hyperscale designs, adds Cadence.
The digital suite and available reference flows help customers achieve better power, performance and area (PPA) while designing on TSMC’s N3 process. Tool suite enhancements include, improved extraction accuracy, updated routing rules, accurate LVF-generation during characterisation and robust support of advanced colouring.
The certification on TSMC’s N3 process includes the Virtuoso Custom IC design platform, consisting of the Virtuoso Schematic Editor, Virtuoso Layout Suite and Virtuoso ADE Product Suite, the Voltus-Fi Custom Power Integrity Solution, and the Spectre Circuit Simulation Platform, which includes the Spectre X Simulator.
Custom enhancements for TSMC’s N3 process technology include expanded 3nm design rule support, custom digital colour remastering, enhanced analogue cell support, additional productivity improvements with an enhanced device-level place and route flow and a front-to-back legacy-node design migration flow.
Suk Lee, senior director of the Design Infrastructure Management Division at TSMC, commented: “Our latest work enables our customers to design with the tools, benefitting from the significant power and performance boost of TSMC’s 3nm process technology and to quickly launch their new product innovations to market.”