Cadence announces support for 7nm Arm Cortex-A76 CPU designs

Full-flow digital and sign off tools from Cadence and the Cadence Verification Suite support the new Arm Cortex-A76 processor for laptops and smartphones (see Arm today’s Arm story).

To accelerate the adoption of Arm’s latest processor, Cadence offers a 7nm Rapid Adoption Kit (RAK) to enable customers to improve power, performance, and area (PPA) and speed time to market.

Cadence has worked closely with Arm to ensure that the Cadence Verification Suite improves overall verification productivity for customers using Cortex-A76.

The 7nm RAK includes comprehensive documentation to enable customers to optimise an Cadence digital implementation flow using the latest tool features to achieve PPA goals when creating Cortex-A76 processor designs.

The Cadence RTL-to-GDS flow incorporates the following digital and signoff tools: Innovus Implementation System using statistical on-chip variation (SOCV) propagation and optimisation to improve timing closure for 7nm designs; Genus Synthesis Solution, the RTL synthesis supports the latest 7nm advanced-node requirements, for convergent design closure using the Innovus Implementation System. There is also Conformal Equivalence Checking to ensure the accuracy of logic changes and engineering change orders (ECOs) during the implementation flow and Conformal Low Power to create and validate the power intent in the context of the design, combining low-power equivalence checking with structural and functional checks to allow full-chip verification of power-efficient designs.

Another component is Tempus Timing Signoff, which offers path-based, sign off-accurate timing analysis and 7nm physically aware ECO design optimisation. It provides the quickest path to tape-out, says Cadence.

Also included is the Voltus IC Power Integrity Solution, where static and dynamic analysis is used during implementation and sign off to ensure optimal power distribution design. Finally, there is Quantus Extraction, which fulfills all 7nm advanced-node requirements to ensure accurate correlation to final silicon.

The Cadence Verification Suite interoperates with the Cortex-A76 processor and includes JasperGold Formal Verification for IP and sub-system verification including formal proofs for Arm AMBA protocols, Xcelium Parallel Logic Simulation to provide production-proven multi-core simulation accelerating SoC development and validation of Arm-based designs, Palladium Z1 Enterprise Emulation Platform includes hybrid technology that is integrated with Arm Fast Models for up to 50X faster OS and software bring-up and up to 10X faster software-based testing in addition to Dynamic Power Analysis technology for low power. Finally, the Verification IP Portfolio enables IP and SoC verification including Arm AMBA interconnect, supporting Xcelium simulation, the JasperGold platform, and the Palladium Z1 platform

A series of seminars will be held during 2018, where customers can learn how to implement Cortex-A76 processors using the Cadence tools. Seminars are being planned in India (Bangalore), China (Beijing and Shanghai), Taiwan (Hsinchu) and Japan (Shin-Yokohama).

Cadence will also be exhibiting at DAC 2018 (24 to 28 June) in San Francisco – booth 1245.

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