Arm expands reach of DesignStart program for Linux

Arm has announced that its DesignStart program now offers fast access to the Cortex-A5 CPU, its lowest-power, Linux-capable application processor.

Now, says the company, developers can accelerate rich-featured embedded and IoT SoC design for applications such as medical, smart home, gateways and wearables.

The program provides a low-cost route to Linux-capable SoCs with affordable IP, and access to middleware and applications that run on Arm.

According to Arm, DesignStart has opened up Arm CPUs to designers, with over 3,000 CPU prototyping downloads in the last 12 months. It says it is taking the program to the next level with the Cortex-A5 processor which is used by cloud vendors as the entry point for edge IoT processing. Access to the Cortex-A5 processor is through a web portal and a simplified contract, speeding up time to market. The Cortex-A5’s small footprint of less than 0.3mm when implemented on a 40nm process, and high efficiency of around 100microW/MHz active power when implemented on a 40nm process, allows for reduced fabrication costs and the lowest idle power among Cortex-A CPUs, claims Arm. It offers between 70 and 80 per cent of the performance of Cortex-A7, Cortex-A9, and Cortex-A32 processors and can be configured as a fully coherent quad-core design with advanced SIMD data processing, and a high-performance accelerator port for fast connection to machine learning or other custom processors.

Arm says it is now providing developers with the lowest cost access to a Linux-capable Arm CPU. IP access, including one-year design support from Arm experts, is $75k, with an alternative option of $150k access fee that includes three years’ support.

The Cortex-A5 will also enable advanced machine learning applications with Arm’s Neural Network inference engine, which is part of Linaro’s Machine Learning Initiative.

The Cortex-A5 package in DesignStart includes flexible system IP for area and power-optimised SoC development. Key benefits of the system IP include a flexible system IP for area and power-optimised SoC development, low-latency interconnect, with Arm CoreLink NIC-400 provides configurable and low-power connectivity with design flexibility, seamless debugging and TrustZone technology for hardware-enforced isolation to establish a secure root of trust.

When ready to tape out a custom chip, time to market can be accelerated with Arm’s Artisan physical IP.

Photo credit: Idea Go

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